1. Field of the Invention
The invention relates to a semiconductor device fabrication method and, more particularly, to a substrate contact formation method.
2. Description of the Related Art
Due to advances in CMOS technology of recent years, the functions of CMOS devices employing bulk Si substrates are improving rapidly. Therefore, applications of CMOS technology in higher frequency regions of the GHz band, which have been conventionally problematic, are becoming feasible. When CMOS technology is applied to high frequency circuits, in such cases the combined mounting of digital and analog circuits may be considered, the performance of the analog circuit is known to deteriorate due to crosstalk noise from the digital circuit.
As compared with a CMOS device employing a bulk Si substrate, an SOI-CMOS device employs an SOI (Silicon On Insulator) substrate which has an insulating layer between a support substrate and an element region. Accordingly, those elements which are formed on the same substrate are completely isolated with respect to each other by means of a buried oxide film, i.e., the insulating layer, which extends below the element region, thereby suppressing crosstalk noise from the digital circuit.
In addition, because a high-resistance Si substrate can be easily adopted as the support substrate in the SOI device, high-frequency signal loss can be suppressed in a passive element such as an on-chip capacitor or an inductor.
In cases where an SOI device is applied to a high-frequency circuit, it is essential to fix the potential of the support substrate at ground potential. This is because, when a noise enters the support substrate, there is a risk that characteristics of the SOI-CMOS device fluctuate under the influence of the noise and that the performance of the analog circuit deteriorates. As a countermeasure against above risk, a method to keep the support substrate at ground potential is generally adopted, which is achieved by forming a substrate contact (See Japanese Patent Application Kokai Nos. 2002-190521, 2000-243967, and 2003-218356, for example). Thus, a conventional formation method of the substrate contact will be described with reference to FIGS. 5 and 6.
First, a CMOS is formed on an SOI substrate by means of a well-known SOI-CMOS fabrication method (See FIG. 5A). Although the CMOS consists of two types of MOSFETs, only one MOSFET (a p-type MOSFET, for example) is shown, but the other MOSFET (an n-type MOSFET, for example) is not shown hereinafter. The SOI substrate includes a support substrate 210, a buried oxide film 220 which is an insulating layer provided on the support substrate 210, and a silicon layer 230 provided on the buried oxide film 220. The silicon layer 230 is isolated from other elements (not shown) provided on the substrate by means of an element isolation insulating layer 252.
In the silicon layer 230, a gate region 234, a drain region 236 and a source region 238 are formed. A drain electrode 286 and a source electrode 288 which are made from a metal silicide using a metal such as cobalt are formed on the drain region 236 and source region 238 of the silicon layer 230, respectively. A gate oxide film 264 is provided on the gate region 234, and a gate electrode 274 is formed on the gate oxide film 264.
Next, an interlayer insulating film 290 is formed on the MOSFET formed in the silicon layer 230 and on the element isolation insulating layer 252. The interlayer insulating film 290 is formed by means of a CVD method, for example (See FIG. 5B).
Next, contact holes are provided above the MOSFET formed on the silicon layer 230 by photolithographically etching the interlayer insulating film 290. The contact holes are provided in positions that correspond with the gate electrode 274, the drain electrode 286 and the source electrode 288, respectively. FIG. 5C shows, by way of example, a drain contact hole 296 provided above the drain electrode 286 and a source contact hole 298 provided above the source electrode 288. In addition, a substrate contact hole 292 is provided by photolithographically etching the interlayer insulating film 290, the element isolation insulating layer 252 and the buried oxide film 220 (see FIG. 5C).
Next, in order to reduce a contact resistance, impurity is introduced into the support substrate via the substrate contact hole 292. Accordingly, a substrate contact region 212 is formed to be a high-density impurity diffusion region (see FIG. 6A). In cases where the substrate contact region 212 is a p-type contact region, p-type impurity such as BF2 or B is introduced and, when the substrate contact region 212 is an n-type contact region, n-type impurity such as As or P is introduced. Thereafter, annealing is performed to activate the substrate contact region 212.
Next, the drain contact hole 296, the source contact hole 298, the gate contact hole (not shown), and the substrate contact hole 292 are filled with tungsten (W) or the like by means of the CVD method so as to form a drain plug 306, a source plug 308, a gate plug (not shown), and a substrate contact plug 302, respectively (see FIG. 6B).
Next, metal (aluminum, for example) wiring is formed on the interlayer insulating film 290 by means of a sputtering method so as to provide a drain wiring 316, a source wiring 318, a gate wiring (not shown), and a substrate wiring 312 (see FIG. 6C). The drain electrode 286 is connected externally via the drain plug 306 and the drain wiring 316, the source electrode 288 is connected externally via the source plug 308 and the source wiring 318, and the gate electrode 274 is connected externally via the gate plug (not shown) and the gate wiring (not shown). The substrate contact region 212 is connected externally via the substrate contact plug 302 and the substrate wiring 312 and is normally held at ground potential.
In SOI device fabrication, a resistance between the substrate contact region and the substrate contact plug (hereinafter also referred to as a contact resistance) must be made low in order to hold the support substrate at ground potential.
In order to reduce the contact resistance, the substrate contact region is doped with impurity by ion implantation. After the ion implantation, annealing is required to activate the impurity. However, when annealing is performed at a temperature of 800° C. or more, adverse effects such as the aggregation of metal silicide formed as the drain electrode 286 and the source electrode 288 occur. On the other hand, in order to activate the substrate contact region adequately and reduce the contact resistance, annealing at a temperature of 1000° C. or more is required, which means annealing at a temperature of 800° C. or less is inadequate. As a result, a low contact resistance is not achieved.
Because the substrate contact hole must be formed deeply, the aspect ratio thereof becomes high and it is therefore sometimes impossible to perform adequate ion implantation in the substrate contact region. Therefore, a plug made from polycrystalline silicon is formed on the substrate contact region in order to reduce the aspect ratio of the substrate contact hole, which is disclosed in Japanese Patent Application Kokai No. 2002-190521.
On the other hand, in order to reduce the number of steps to introduce the impurity, the impurity introduction to the substrate contact region via the substrate contact hole is performed simultaneously with the impurity introduction to the source and drain regions of the MOSFET, which is disclosed in Japanese Patent Application Kokai Nos. 2000-243967 and 2003-218356.
However, in Japanese Patent Application Kokai No. 2002-190521, a step of forming a polycrystalline silicon layer in the substrate contact region is additionally required. Further, in Japanese Patent Application Kokai Nos. 2000-243967 and 2003-218356, a step of forming an opening for substrate contact formation is required after the formation of an element isolation region. As described above, the step to achieve the low contact resistance is complex in any conventional technology.